US 7,430,578 B2
Method and apparatus for performing multiply-add operations on packed byte data
Eric Debes, Santa Clara, Calif. (US); William W. Macy, Palo Alto, Calif. (US); Jonathan J. Tyler, Austin, Tex. (US); James Coke, Shingle Springs, Calif. (US); Frank Binns, Hillsboro, Oreg. (US); Scott Rodgers, Hillsboro, Oreg. (US); Peter Ruscito, Folsom, Calif. (US); Bret Toll, Hillsboro, Oreg. (US); Vesselin Naydenov, Folsom, Calif. (US); Masood Tahir, Orangevale, Calif. (US); and David Jackson, Folsom, Calif. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Jun. 30, 2003, as Appl. No. 10/610,831.
Application 10/610831 is a continuation in part of application No. 09/952891, filed on Oct. 29, 2001, granted, now 7,085,795.
Prior Publication US 2004/0073589 A1, Apr. 15, 2004
Int. Cl. G06F 7/38 (2006.01)
U.S. Cl. 708—603 32 Claims
OG exemplary drawing
 
1. A method for processing digital video, image or audio signal data elements, the method comprising:
decoding a plurality of instructions including a multiply-add instruction of a variable length instruction format comprising a first and a second opcode field, an addressing mode field, a first source field to indicate a first operand, the first operand having a first plurality of byte data elements including at least A1, A2, A3, and A4 byte data elements, and second source field to indicate second operand having a second plurality of byte data elements including at least B1, B2, B3, and B4 byte data elements;
determining a length of the multiply-add instruction from said first opcode field, said addressing mode field, and optionally from said first source field, said second source field and an optional base field; and
responsive to said second opcode field, enabling an execution unit with the decoded multiply-add instruction to perform the operation (A1×B1)+(A2×B2) to generate a first 16-bit data element of a packed result data, and to perform the operation (A3×B3)+(A4×B4) to generate a second 16-bit data element of the packed result data.