| US 7,373,536 B2 | ||
| Fine granularity halt instruction | ||
| Hiroo Hayashi, Round Rock, Tex. (US) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 04, 2004, as Appl. No. 10/911,418. | ||
| Prior Publication US 2006/0031704 A1, Feb. 09, 2006 | ||
| Int. Cl. G06F 1/00 (2006.01) | ||
| U.S. Cl. 713—323 [713/400; 713/500; 712/206; 712/208] | 29 Claims |
| 1. A method of halting instruction execution in a microprocessor, comprising:
executing instructions associated with a first thread and a second thread in the microprocessor according to a first clock;
receiving an instruction, wherein the instruction is associated with the first thread and specifies a source of a second clock
and a number of cycles, wherein the first clock and the second clock are different speeds; and
halting the execution of instructions associated with the first thread for the number of cycles of the specified second clock
while continuing to execute instructions associated with the second thread according to the first clock.
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