| US 7,372,744 B2 | ||
| Memory system which copies successive pages, and data copy method therefor | ||
| Hitoshi Shiga, Yokohama (Japan); Chih-Chung Chen, Jubei (Taiwan); Chih-Hung Wang, Jubei (Taiwan); and Sheng-Lin Hung, Jubei (Taiwan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan); and Solid State System Co., Ltd., Jubei (Taiwan) | ||
| Filed on Sep. 01, 2005, as Appl. No. 11/216,215. | ||
| Claims priority of application No. 2004-257565 (JP), filed on Sep. 03, 2004. | ||
| Prior Publication US 2006/0050314 A1, Mar. 09, 2006 | ||
| Int. Cl. G11C 7/10 (2006.01) | ||
| U.S. Cl. 365—189.05 [365/185.12; 365/185.17] | 19 Claims |
| 1. A memory system comprising:
a memory cell array in which electrically rewritable nonvolatile memory cells are arrayed;
a first data buffer which holds, in read, data read from the memory cell array via a bit line switch and in write, data to
be written in the memory cell array via the bit line switch;
a second data buffer which is configured to swap data with the first data buffer, copies data to the first data buffer, and
receives a copy of data from the first data buffer;
a bus switch which is interposed between the second data buffer and a bus, selects part of data held by the second data buffer,
and transfers the part of data to the bus;
an error correction circuit which is connected to the bus and performs error correction calculation of data read from the
memory cell array; and
a control circuit which controls the bit line switch, the first data buffer, and the second data buffer, sequentially reads,
page by page, at least one page from an mth (m is a positive integer) page to an nth (n is an integer greater than m) page
of a first block in the memory cell array, controls the error correction circuit to perform error correction calculation by
the error correction circuit, controls the first data buffer, the second data buffer, and the bit line switch, and controls
to perform write in a second block in an erase state in the memory cell array.
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