| US 7,370,810 B2 | ||
| Semiconductor device and memory card having the same | ||
| Nobuyoshi Nara, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 31, 2006, as Appl. No. 11/513,025. | ||
| Application 11/513025 is a continuation of application No. PCT/JP2005/017429, filed on Sep. 15, 2005. | ||
| Claims priority of application No. 2004-291661 (JP), filed on Oct. 04, 2004. | ||
| Prior Publication US 2006/0289660 A1, Dec. 28, 2006 | ||
| Int. Cl. G06K 19/05 (2006.01) | ||
| U.S. Cl. 235—492 [235/380] | 14 Claims |
| 1. A semiconductor device to be applied to a memory card, comprising:
a first circuit which operates in accordance with an internal clock;
a second circuit which generates information of which an external apparatus is to be notified;
an interface section which notifies the external apparatus of the information generated by the second circuit without using
the first circuit upon receiving a predetermined command from the external apparatus before the memory card enters a standby
state; and
a plurality of terminals each of which is connectable to one of power terminals and ground terminals provided on a substrate,
the information being determined depending on whether each of the plurality of terminals is electrically connected to the
power terminal or ground terminal on the substrate.
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